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U2731B
DAB One-Chip Front End
Description
The U2731B is a monolithically integrated DAB one-chip front end circuit manufactured using Atmel Wireless & Microcontrollers' advanced UHF5S technology. Its functionality covers a gain-controlled RF amplifier with two selectable RF inputs, a gain-controlled RF mixer, a VCO which provides the LO signal for the RF mixers, either directly or after passing a frequency divider, a SAW filter driver, an AGC block for the RF section, a gain-controlled IF amplifier, an IF mixer which can also be bypassed, an AGC block for the IF section and a fractional-N frequency synthesizer. The frequency synthesizer controls the VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a 16-kHz raster; within certain limits the reference divide factor is fully programmable. The lock status of the phase detector is indicated at a special output pin; three switching outputs can be addressed. A reference signal which is generated by an on-chip reference oscillator is available at an output pin. This reference signal is also used to generate the LO signal for the IF mixer, either by doubling the frequency or by using the reference frequency itself. Three D/A converters at a resolution of 8 bits provide a digitally controllable output voltage. The thresholds inside the AGC blocks can be digitally controlled by means of on-chip 4-bit D/A converters. All functions of this IC are controlled by the I2C bus. Electrostatic sensitive device. Observe precautions for handling.
Features
D 8.5 V supply voltage D Voltage regulator for stable operating conditions D Microprocessor controlled via an I2C bus D 4 addresses selectable D Gain-controlled RF amplifier with two inputs, selectable by I2C-bus control D Balanced RF amplifier inputs D Gain-controlled RF mixer D Four-pin voltage-controlled oscillator D SAW filter driver with differential low-impedance output D AGC voltage generation for RF section, available at charge-pump output (can also be used to control a PIN diode attenuator) D Gain-controlled IF amplifier D Balanced IF amplifier inputs D Selectable gain-controlled IF mixer D Single-ended IF output D AGC voltage generation for IF section, available at charge-pump output D Separate differential input for the IF AGC block D All AGC time constants adjustable D AGC thresholds programmable via the I2C bus D Three AGC charge pump currents selectable (zero, low, high) D Reference oscillator D Programmable 9-bit reference divider D Programmable 15-bit counter 1:2048 to 1:32767 effectively D Tristate phase detector with programmable charge pump D Superior phase-noise performance D Deactivation of tuning output programmable D 3 switching outputs (open collector) D 3 D/A converters (resolution: 8 bits) D Lock status indication (open collector)
Ordering Information
Extended Type Number U2731B-MFN U2731B-MFNG1 Package SSO44 SSO44 Tube Taped and reeled Remarks
Rev. A2, 09-Oct-00
1 (20)
Preliminary Information
U2731B
Block Diagram
SAW1 SAW2 18 19 IFIN1 IFIN2 24 23 CPIF 28 26 27 IF AGCIN2 IF AGCIN1 21 SLI 22 WAGC
CPRF
16
th1
th3
VAGC
th2
RFA1 RFA2 12 13
VAGC
29 RFB1 RFB2 32 33 34 35 14 15 IFOUT
C1VCO B2VCO B1VCO C2VCO
VCO
1/ 2
x1/x2
20, 25, 38
D/A
D/A
D/A
10, 11, 17, 30, 31,36, 37
VS
GND
4-bit latch
4-bit latch
4-bit latch
4-bit latch
Lock detector
42 OSCI 43 OSCO 5 FREF
41 PLCK 39 PD
Reference counter
Tristate phase detector
Programmable charge pump
40 VD
Fractional-N control
Programmable 13-bit counter N/N+1
4-bit latch
3-bit latch
8-bit latch
8-bit latch
8-bit latch
9-bit latch
15-bit latch
MUX
MUX
I2 C bus-interface/control
44 ADR 1 SCL 2 SDA
Switches
3 6 4
D/A
7 CAO
D/A
8 CBO
D/A
9 CCO
15037
SWA SWC SWB
Figure 1. Block diagram
2 (20)
Rev. A2, 09-Oct-00
Preliminary Information
U2731B
SCL SDA SWA SWB FREF SWC CAO CBO CCO GND GND RFA1 RFA2 RFB1 RFB2 CPRF GND SAW1 SAW2 VS SLI WAGC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
14855
44 43 42 41 40 39 38 37 36 35 34 33 32
ADR OSCO OSCI PLCK VD PD VS GND GND C2VC B1VCO B2VCO C1VC
31 GND 30 GND 29 IFOUT 28 CPIF
27 IFAGCIN1 26 IFAGCIN2 25 VS 24 23 IFIN1 IFIN2
Figure 2. Pinning
Rev. A2, 09-Oct-00
Preliminary Information
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1 2 3 4 5 6 7 8 9 SCL Clock (I2C bus) Data (I2C bus) SDA SWA Switching output (open collector) Switching output (open collector) Switching output (open collector) Output of D/A converter A Output of D/A converter B Output of D/A converter C Ground SWB SWC CAO CBO CCO FREF Ref. frequency output (for U2730B) 10AAAAGround GND 11 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 42 43 44 RFA1 RFA2 Input 1 of RF amplifier A (differential) Input 2 of RF amplifier A (differential) Input 1 of RF amplifier B (differential) Input 2 of RF amplifier B (differential) Charge-pump output (RF AGC block) Ground SAW driver output 1 (differential) SAW driver output 2 (differential) Supply voltage AGC mode selection (charge-pump current high) AGC mode selection (charge-pump current off) RFB1 RFB2 GND CPRF SAW1 SAW2 VS SLI WAGC IFIN2 IFIN1 VS Input 2 of IF amplifier (differential) Input 1 of IF amplifier (differential) Supply voltage IFAGCIN2 Input 2 of IF AGC block (differential) IFAGCIN1 Input 1 of IF AGC block (differential) CPIF Charge-pump output (IF AGC block) IF output (single ended) Ground IFOUT GND 30AAAAGround GND C1VC Collector 1 of VCO Base 2 of VCO Base 1 of VCO Ground Ground B2VCO B1VCO C2VC GND GND VS PD Collector 2 of VCO Supply voltage Tristate charge pump output Active-filter output VD PLCK OSCI ADR Lock-indicating output (open collector) Input of reference oscillator/buffer Address selection (I2C bus) Output of reference oscillator/buffer OSCO
Pin Description
Pin
Symbol
Function
3 (20)
U2731B
Functional Description
The U2731B-A represents a monolithically integrated front end IC designed for applications in DAB receivers. It covers RF and IF signal processing, the PLL section and also supporting functions such as D/A converters or switching outputs. Two RF input ports offer the possibility of handling various input signals such as a down-converted L-band signal or band II and band III RF signals. The high dynamic range of the RF inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in the RF section offer the possibility of even strong RF input signals. The LO signal of the first mixer stage is derived from an on-chip VCO. The VCO frequency is either divided by two or directly fed to the mixer. In this way band II and band III can be covered easily. In the IF section, it can be selected if the first IF signal is down-converted to a second, lower IF or if it is simply amplified to appear at the IF output. If the downconversion option is chosen, it can be selected if the LO signal of the IF mixer is directly derived from the reference signal of the PLL, or if it is generated by doubling its frequency. The amplifiers in the IF section are gain-controlled in similar fashion to the RF section. The RF and the IF part also contain AGC functional blocks which generate the AGC control voltages. The AGC thresholds can be defined by means of three on-chip 4-bit D/A converters. The frequency of the VCO is locked to a reference frequency by an on-chip fractional-N PLL circuit which guarantees a superior phase-noise performance. The reference frequency is generated by an on-chip crystal oscillator which can also be overdriven by an external signal. Starting from a minimum value, the reference scaling factor is freely programmable. Three switching outputs can be used for various switching tasks on the front end board. Three 8-bit D/A converters providing an output voltage between 0 and 8.5 V are used to improve the tuning voltages of the tuned preselectors which are derived from the tuning voltage of the VCO. All functions of this circuit are controlled by an I2C bus.
RF Part
RF Gain-Controlled Amplifier
In order to support two different channels, two identical input buffers with balanced inputs (RFA1, RFA2; RFB1, RFB2) are integrated. By setting the I2C bus bits M0 and M1 (see section `I2C-bus functions'),the active buffer can be selected. The buffers are followed by a gain-controlled amplifier whose output signal is fed to a gain-controlled mixer. The RF amplifiers are capable of handling input signals up to a power of -6 dBm without causing third-order intermodulation components stronger than -40 dBc.
RF Gain-Controlled Mixer, VCO and LO Divider
The purpose of the RF mixer is to down-convert the incoming signal (band II, band III) to an IF frequency which is typically 38.912 MHz. This IF signal is fed to an AGC voltage-generation block (which is described in the following section) and an output buffer stage. This driver stage has a low output impedance and is capable to drive a SAW filter directly via its differential output Pins SAW1, SAW2. The mixer's LO signal is generated by a balanced voltage-controlled oscillator whose frequency is stabilized by a fractional-N phase-locked loop. An example circuit of the VCO is shown in figure 12. The oscillator 's tank is applied to the Pins B1VC, C1VC, B2VC, C2VC as shown in the application circuit in figure 6. Before the VCO's signal is fed to the RF mixer, it has to pass an LO divider block where the VCO frequency is either divided by 1 or 2. The setting of this divider is defined by means of the I2C-bus bits M0 and M1 as indicated in the section `I2C-bus functions'. This feature offers the possibility of covering both band II and band III by tuning the VCO frequency in the range between 200 MHz to 300 MHz.
4 (20)
Rev. A2, 09-Oct-00
Preliminary Information
U2731B
RF AGC Voltage-Generation Block
In this functional block, the output signal of the RF mixer is amplified, weakly bandpass filtered (transition range: X8 MHz to X80 MHz), rectified and finally lowpass filtered. The voltage derived in this `power-measurement process' is compared to a voltage threshold (th1) which can be digitally controlled by an on-chip 4-bit D/A converter. The setting of this converter is defined by means of the I2C-bus bits TAi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump feeds a positive or negative current to Pin CPRF in order to charge or discharge an external capacitor. The voltage of this external capacitor can be used to control the gain of an external preamplifier or attenuator stage: Furthermore, it is also used to generate the internal control voltages of an RF amplifier and mixer. For this purpose, the voltage at Pin CPRF is compared to a voltage threshold (th2) which is also controlled by an on-chip 4-bit D/A converter whose setting is fixed by the I2C-bus bits TBi (i =1, 2, 3, 4). By means of the input Pins WAGC and SLI the current of the RF AGC charge pump can be selected according to the following table:
IF Gain-Controlled Amplifier/Mixer Combination
Depending on the setting of the I2C-bus bits M2, M3, the output signal of the gain-controlled IF amplifier is either mixed down to a lower, second IF or, after passing an output buffer stage, amplified before it appears at the single-ended output Pin IFOUT. If the down-conversion option is chosen this circuit still offers two possibilities concerning the synthesis of the IF mixers LO signal. This LO signal is derived from the PLL's on-chip reference oscillator. By means of the I2C-bus bits M2, M3, it can be decided whether the reference frequency is doubled before it is given to the mixer's LO port, or if it is used directly. The gain-control voltage of the amplifier/mixer combination is similar to the gain-controlled IF amplifier generated by an internal gain-control circuit.
IF AGC Voltage-Generation Block
The purpose of this gain-control circuit in the IF part is to measure the power of the incoming signal at the balanced input Pins IFAGCIN1, IFAGCIN2, to compare it with a certain power level and to generate a control voltage for the IF gain-controlled amplifiers and mixer. This architecture offers the possibility of ensuring an optimal use of the dynamic range of the A/D converter which transforms the output signal at Pin IFOUT from the analog to the digital domain despite possible insertion losses of (anti-aliasing) filters which are arranged in front of the converter. Such a constellation is indicated in the application circuit in figure 6. The incoming signal at the balanced input Pins IFAGC1, IFAGC2 passes a `power-measurement process' similar to that described in the section `RF AGC VoltageGeneration Block'. For flexibility reasons, no bandpass filtering is implemented. The voltage derived in this process is compared to a voltage threshold (th3) which is defined by an on-chip 4-bit D/A converter. The setting of this converter is defined by the I2C-bus bits TCi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump feeds a positive or negative current to Pin CPIF in order to charge or discharge an external capacitor. By means of the Pins WAGC and SLI the current of this charge pump can be selected according to the following table:
Rev. A2, 09-Oct-00
Preliminary Information
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AAAAAAAAAAA A A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAA AA
The block functionality can be seen in figure 10.
WAGC HIGH LOW LOW
SLI X LOW HIGH
Charge-Pump Current / mA off 50 mA (slow mode) 190 mA (fast mode)
IF Part
IF Gain-Controlled Amplifier
The signal applied to the balanced input Pins IFIN1, IFIN2 is amplified by a gain-controlled IF amplifier. The gain-control signal is generated by an IF AGC voltagegeneration block which is described in the next section. To avoid offset problems, the output of the gain-controlled amplifier is fed to an amplifier/mixer combination by AC coupling.
WAGC HIGH LOW LOW
SLI X
Charge Pump Current / mA off 50 mA (slow mode)
LOW
HIGH
190 mA (fast mode)
The block functionality can be seen in figure 11.
5 (20)
U2731B
PLL Part
The purpose of the PLL part is to perform a phase lock of the voltage-controlled RF oscillator to an on-chip crystal reference oscillator. This is achieved by means of a special phase-noise-shaping technique based on the fractional-N principle which is already used in Atmel Wireless & Microcontrollers's U2733B frequency synthesizer series. It concentrates the phase detector's phase-noise contribution to the spectrum of the controlled VCO at frequency positions where it does not impair the quality of the received DAB signal. A special property of the transmission technique which is used in DAB is that the phase-noise-weighting function which measures the influence of the LO's phase noise to the phase information of the coded signal in a DAB receiver has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines, the DAB signal is not impaired as long as these lines do not exceed a set limit. For DAB mode I, this phase-noise-weighting function is shown in figure 3:
1,80 1,60 1,40 1,20 1,00 0,80 PNWF 0,60 0,40 0,20 0,00 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
Reference Divider
Starting from a minimum value, the scaling factor SFref of the 9-bit reference divider is freely programmable by means of the I2C-bus bits ri (i = 0, ..., 8) according to SFref = ri x 2i. If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the reference divider has to be specified in such a way that the division process results in an output frequency which is four times higher than the desired frequency raster, i.e., the comparison frequency of the phase detector equals four times the frequency raster. By changing the division ratio of the main divider from N to N+1 in an appropriate way (fractional-N technique), this frequency raster is interpolated to deliver a frequency spacing of 16 kHz. So effectively a reference scaling divide factor SFref,eff = 4 x ri x 2i is achieved. By setting, the I2C-bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWA.
Main Divider
The main divider consists of a fully programmable 13-bit divider which defines a division ratio N. The applied division ratio is either N or N+1 according to the control of a special control unit. On average, the scaling factors SF = N + k/4 can be selected where k = 0, 1, 2, 3. In this way, VCO frequencies fVCO = 4 x (N+k/4) x fref / (4 x SFref) can be synthesized starting from a reference frequency fref. If we define SFeff = 4 x N + k and SFref,eff = 4 x SFref (previous section), then fVCO = SFeff x fref / SFref,eff, where SFeff is defined by 15 bits. In the following, this circuit is described in terms of SFeff and SFref,eff. SFeff has to be programmed via the I2C-bus interface. An effective scaling factor from 2048 to 32767 can be selected by means of the I2C-bus bits ni (i = 0, ..., 14) according to SFeff = ni x 2i. By setting the I2C-bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWC. When the supply voltage is switched on, both the reference divider and the programmable divider are kept in RESET state until a complete scaling factor is written onto the chip. Changes in the setting of the programmable divider become active when the corresponding I2C bus transmission is completed. An internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the output frequency without restricting the controlled VCO's frequency spectrum.
df / Hz
Figure 3.
It is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. The technique of concentrating the phase noise in the positions of such zeros is protected by a patent.
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. As already described in the section `IF Gain-Controlled Amplifier/ Mixer Combination', the LO signal for the mixer in the IF section is derived. By applying a crystal to the Pins OSCI, OSCO, figure 7, this oscillator generates a highly stable reference signal. If an external reference signal is available, the oscillator can be used as an input buffer. In such an application, see figure 8, the reference signal has to be applied to the Pin OSCI and the Pin OSCO must be left open.
6 (20)
Rev. A2, 09-Oct-00
Preliminary Information
U2731B
Phase Comparator and Charge Pump
The tristate phase detector causes the charge pump to source or to sink current at the output Pin PD depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. Four different values of this current can be selected by means of the I2C-bus bits I50 and I100. By use of this option, changes of the loop characteristics due to the variation of the VCO gain-as a function of the tuning voltage can be reduced. The charge-pump current can be switched off using the I2C-bus bit TRI. A change in the setting of the charge pump current becomes active when the corresponding I2C-bus transmission is completed. As described for the setting of the scaling factor of the programmable divider, an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a change in the charge pump current without restricting the controlled VCO's frequency spectrum. A high-gain amplifier (output pin: VD), which is implemented in order to construct a loop filter as shown in the application circuit, can be switched off by means of the I2C bus-bit OS. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is detected, the open collector output Pin PLCK is set H (logical value!). It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the I2C-bus bit TRI is set H, the lock detector function is deactivated and the logical value of the PLCK output is undefined.
D/A Converters
Three D/A converters, A, B and C, offer the possibility of generating three output voltages at a resolution of 8 bits. These voltages appear at the output Pins CAO, CBO and CCO. The converters are controlled via the I2C-bus interface by means of the control bits CA0, ..., CA7, CB0, ..., CB7 and CC0, ..., CC7 respectively as described in the section `I2C-Bus Instruction Codes'. The output voltages are defined as VCAO = VM /128 x CAj x 2j, j = 0, .., 7 VCBO = VM /128 x CBj x 2j, j = 0, .., 7 VCCO = VM /128 x CCj x 2j, j = 0, .., 7 where VM = 4.25 V nominally. Due to the rail-to-rail outputs of these converters, almost the full voltage range from 0 to 8.5 V can be used. A common application of these converters is the digital synthesis of control signals for the tuning of preselectors.
I2C-Bus Interface
Via its I2C-bus interface, various functions can be controlled by a microprocessor. These functions are outlined in the following sections `I2C-bus Instruction Codes' and `I2C-bus Functions'. The programming information is stored in a set of internal registers. By means of the Pin ADR, four different I2C-bus addresses can be selected as described in the section `Electrical characteristics'. In figure 4, the I2C-bus timing parameters are explained, figure 5 shows a typical I2Cbus pulse diagram.
Switching Outputs
Three switching outputs controlled by the I2C-bus bits SWA, SWB, SWC can be used for any switching task on the front end board. The currents of these outputs are not limited internally. They have to be limited by external circuit.
Rev. A2, 09-Oct-00
7 (20)
Preliminary Information
U2731B
I2C-Bus Instruction Codes
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Address byte A byte 1 A byte 2 A byte 3 B byte 1 B byte 2 B byte 3 C byte 1 C byte 2 C byte 3 1 0 1 0 0 0 0 AS1 n14 n8 n2 AS2 n13 n7 n1 0 X X X n12 n6 n0 X X 0 X X 1 n11 n5 X r5 r1 X n10 n4 r8 r4 r0 X n9 n3 TA3 TA2 TA1 TA0 r7 r3 1 r6 r2 0 TB3 TC3 X TB2 TC2 X TB1 TC1 X TB0 TC0 X CA7 CB7 1 CA6 CB6 1 CA5 CB5 0 CA4 CB4 OS X CA3 CB3 T M3 CA2 CB2 TRI M2 CA1 CB1 I100 M1 CA0 CB0 I50 M0 D byte 1 D byte 2 D byte 3 SWA CC7 SWB CC6 SWC CC5 CC4 CC3 CC2 CC1 CC0
Description
MSB
LSB
I2C-Bus Functions
AS1, AS2 ni ri TAi
define the I2C-bus address
I50 and I100 define the charge pump current: I50 LOW LOW I100 LOW LOW Charge-Pump Current (nominal) / mA 50 102 151 203
scaling factor (SFref,eff) of the reference divider SFref,eff = 4 x ri 2i define the setting of a 4-bit D/A converter controlling the threshold, th1, of the RF AGC to adjust the controlled output power. define the setting of a 4-bit D/A converter controlling the threshold, th2, which determines the activation voltage for the internal RF AGC. define the setting of a 4-bit D/A converter controlling the threshold, th3, of the IF AGC to adjust the output power.
TBi
TCi
CAi, CBi, CCi OS T
define the setting of the three D/A converters A, B and C (i = 0, ..., 7)
OS = HIGH switches off the tuning output
for T = HIGH, reference signals describing the output frequencies of the reference divider and programmable divider are monitored at SWA (reference divider) and SWC (programable divider). TRI = HIGH switches off the charge pump
TRI
8 (20)
Preliminary Information
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AAAAAAAAAA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAA A
HIGH HIGH HIGH HIGH Mi defines the operation mode:
M3 M2 M1 X X X X M0 X X X X Mode LOW LOW LOW LOW X X X X fLO,IFMIX = fref HIGH HIGH fLO,IFMIX = 2 x fref fLO,IFMIX = 2 x fref HIGH HIGH X X X X IF mixer switched off RF mixer A active, fLO,RFMIX = fVCO RF mixer A active, fLO,RFMIX = fVCO RF mixer B active, fLO,RFMIX = fVCO LOW LOW LOWAAA HIGH LOW HIGH HIGH HIGH RF mixer B active, fLO,RFMIX = fVCO/2
effective scaling factor (SFeff) of the main divider SFeff = ni 2i
SWa SWa = HIGH switches on the output current (a = A, B, C)
Rev. A2, 09-Oct-00
U2731B
I2C-Bus Data Transfer
Format: START - ADR - ACK - - STOP The consists of a sequence of A bytes, B bytes, C bytes and D bytes each followed by ACK. Always a triplet of these bytes (A, B, C or D) has to be completed before a new triplet is started. If no new triplet is started the transmission can be finished before the current triplet is finished. Examples: START - ADR - ACK - DB1 - ACK - DB2 - ACK - DB3 - ACK - CB1 - ACK - CB2 - ACK - CB3 - ACK - AB1 - ACK - AB2 - ACK - AB3 - ACK - BB1 - ACK - BB2 - ACK - BB3 - ACK - STOP START - ADR - ACK - CB1 - ACK - CB2 - ACK - STOP
Stop Start
However: START - ADR - ACK - DB1 - ACK - CB1 -ACK - STOP is not allowed. Description: START STOP ACK ADR aBi start condition stop condition acknowledge address byte a byte i (a =A, B, C, D; i=1,2,3)
I2C-Bus Timing
The values of the periods shown are specified in the section `Electrical Characteristics'. More detailed information can be taken from `Application Note 1.0 (I2C-Bus Description)'. Please note: due to the I2C-bus specification, the MSB of a byte is transmitted first, the LSB last.
Start Stop
SDA tbuf tr tf thdstat
SCL
thdsta
tlow
thddat
thigh
tsudat
tsusta
tsustp
15038
Figure 4. I2C-bus timing
Typical Pulse Diagram
START SDA SCL ADDRESS BYTE ACK A BYTE 1 ACK A BYTE 2 ACK
A BYTE 3 SDA SCL
ACK
C BYTE 1
ACK
C BYTE 2
ACK STOP
15039
Figure 5. Typical pulse diagram
Rev. A2, 09-Oct-00
9 (20)
Preliminary Information
AA A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AAAAA AAAAAAAAAAAAAAA A AAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAA AAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A A A AA A AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AAAA A A AA A AAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AA A
Absolute Maximum Ratings
Thermal Resistance
Operating Range
U2731B
10 (20) Junction ambient Ambient temperature range Supply voltage PLCK output current PLCK output voltage Switch output current Switch output voltage Address select voltage SDA output current I2C-bus Reference input voltage (AC) Differential input IF AGC block Differential input IF amplifier Differential base input VCO SLI input voltage WAGC input voltage Ext. applied voltage at RF charge pump output Pin 16 Differential input RF amplifier Storage temperature Junction temperature Supply voltage input / output voltage Parameters Parameters Parameters SSO44 mod. Pins 1 and 2 Pins 3, 4 and 6 Pins 14 and 15 Pins 33 and 34 Pins 23 and 24 Pins 26 and 27 Pins 12 and 13 Pin 41 Pin 28 Pin 41 Pin 44AAAAA-0.3AAAA ADRAAAA Pin 2 Pin 21AAAAA-0.3AAAA VSLI Pin 22 Pin 42 VIFAGCIN VRFB1,2 VRFA1,2 Symbol VWAGC VCPRF PLCK PLCK VBiVC VOSCI VCPIF VIFIN SWa SWaAAAA -0.3AAAA SCL, SDA SDA Symbol Symbol Tstg VS Tj RthJA Tamb VS Min. -0.3 -0.3 -0.3 -0.3 -40 0.5 0.5 4 -40 to +85 8.0 to 9.35 Value Value t.b.d. Typ.
Preliminary Information
Rev. A2, 09-Oct-00 Max. +150 +9.5 6.25 6.75 500 500 500 500 500 150 0.5 5.5 9.5 5.5 5.5 5.5 5.5 5 1 K/W Unit Unit mVrms mVrms mVrms mVrms mVrms Unit Vpp mA mA mA C C V V V V V V V V V C V
AAA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AAAAAA AAAA AAAAAAAAAA AAAAAAA AA A A AA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAA AA A A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA AAA AA A A A A AA A AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AAAAAAA AAAA AAAAAAAAAA AAAAAAA AA AAA AA A A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA AAA AAAAAA AAAA AAAAAAAAAA AAAAAAA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA AAAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AAAA AAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AAAAAAA AAAAA AAAAAAAAA AAAAAAAA A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A AA AAA AA A A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AAAAAAA AAAA AAAAAAAAAA AAAAAAAA AA A A AA AAA AA A A A AAA A A AA A AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A AA A A A AAAAAAAAA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA A AA A A A AA AAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AA AAAAAAAAAAA AAAA AAAAAAAAAA AAAAAAA AAAAAAAAAAAA AAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C
Rev. A2, 09-Oct-00
Electrical Characteristics
Output power, differential; RL (SAW1, SAW2) > 200 W, TAi = `0000' Pins 18 and 19 AGC threshold (th1) Output power, differential upper limit (TAi = `1111') controlled by I2C-bus bits TAi; lower limit (TAi = `0000') RL (SAW1, SAW2) = 200 W
Maximum output power level
Output frequency range for AGC-voltage generation
Input impedance
Input frequency range
Maximum input power level
Noise figure (double side band)
AGC range RF
Voltage gain
RF part
Maximum supply current
Minimum supply current
Supply voltage
Overall characteristics
Parameters
Single ended,
RFA1, (RFB1) SAW1, SAW2; NFDSB,RF RFA2, RFB2 blocked Pins 12 (14) 19 Differential, 3rd order intermoduPin,max,MIX lation distance 40 dBc, Pout = -19 dBm, TAi = `0000', RL (SAW1, SAW2) = 200 W Pins 12 and 13 (14 and 15) Pins 12 and 13 (14 and 15) fin,RF
RFA1, RFA2; (RFB1, RFB2) SAW1, SAW2, (see figure 9) Pins 12 (14) 18, 19
3.4 V < V(CPRF) = V(CPIF) < 3.6 V; M3 = M2 = HIGH; M1 = M0 = LOW; TAi = TCi = `0000'; TBi = `1000'; SWA = LOW; SWB = LOW; SWC = LOW; TRI = LOW; PLCK = LOW; I100 = I50 = LOW; V(ADR) = open; SLI = LOW; WAGC = HIGH
V(CPRF) = V(CPIF) < 0.8 V; M3 = M2 = HIGH; M1 = M0 = LOW; TAi = TCi = `0000'; TBi = `1000'; SWA = SWB = SWC = LOW; TRI = LOW; PLCK = LOW; I100 = I50 = LOW; V(ADR) = open; SLI = LOW; WAGC = HIGH
Test Conditions / Pins
Preliminary Information
Pins 20, 25 and 38 Pin 18 and 19 Pin 12 (14) fout,SAW Symbol pTH,RF Zin,RF GV,RF IS,max IS,min VS Min. 8.0 70 38,912 MHz 5 -7AAAAdBm Typ. -8 -22 -10 1.3 8.5 12AAAA dB 27 26 79 74
U2731B
Max.
9.35
260
11 (20) MHz dBm dBm dBm Unit mA mA k dB dB V
AAA A A A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAAAA AAAAAAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A A AAA A A A A AA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAA A A A A AA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA AAA A A A AAAAAAAAA AAAAA AAAAAAAAA AAAAAAAA A AAAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAA AAA AA AA AAAAA AAAAAAAAA AAAAAAA A AAA A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A A AAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAA A A AAA A A A A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AA A A AAA A A A A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAA A A A A AA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAA A A A A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAA A A A A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAA A A A A AA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAA A A A A A AAAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAA AAA AA AA AAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A AAAA AAA AA AAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAA AAAAAAAAA AAAAAAA A A AAA A A A A AA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA AAAAAAA AAAAAA AAAAAAAAA AAAAAA A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA A A A AAAAAAAAAA AAAAA AAAAAAAAA AAAAAAA A AAA AAA A A
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C
Electrical Characteristics (continued)
U2731B
12 (20) VCO
Negative charge pump current, slow mode
Positive charge pump current, slow mode
Ngative charge pump current, fast mode
Positive charge pump current, fast mode
RF AGC unit
Output impedance
Output frequency range
Input impedance
Input frequency range
Maximum input power level
Noise figure (double side band)
AGC range IF
Voltage gain
Voltage gain
IF part
Phase noise
Output impedance
AGC threshold (th2) (internal AGC) upper limit (TBi = `1111') lower limit (TBi = `0000')
Parameters
VWAGC = LOW, VSLI = LOW
VWAGC = LOW, VSLI = LOW
VWAGC = LOW, VSLI = HOGH
VWAGC = LOW, VSLI = HIGH
Single ended Pin 28 fout,IFO (3 MHz) fout,IFO (20 MHz) fout,IFO (38.9 MHz)
Single ended
IFIN2 blocked, fIF,IFIN = 38.912 MHz Pins 23 and 24
IFIN2 blocked, 3rd order intermodulation distance 40 dBc; RL(IFOUT) = 1 k; TCi = `0000'; R10 = 4.7 k, R11 = 1.8 k Pin 24
IFIN2 blocked,
IFIN2 blocked, (see figure 9) IF mixer switched off Pin 24 29
IFIN2 blocked, (see figure 9) fLO,IFMIX = fref or FLO,IFMIX = 2 x fref Pin 24 29
Df = 10 kHz
Single ended; f(SAW1) = 39 MHz, Pin 18 (19)
Controlled by PIN,MAX = -25 dBm
Test Conditions / Pins
Preliminary Information
I2C-bus Pins 23 and 24 Pin 24 29 Pin 28 Pin 16 Pin 16 bits TBi; ICPRFNEG, SM ICPRFNEG, FM ICPRFPOS, SM ICPRFPOS, FM Vint AGC,RF Zout,IFOUT Zout,SAW Symbol Zin,IFIN fout,IFO NFDSB Pin,max fin,IFIN GV,tot GV,tot L(f) fLO Min. -220 -52 145 100 38 10 45 42 1 20+j50 65+j35 58-j25 600 - j1000 -180 Typ. -40 180 -20 -88 5.1 1.6 40 44 47 44 30 11 Rev. A2, 09-Oct-00 Max. -145 -38 220 400 52 45 60 49 46 dBc/Hz MHz MHz MHz dBm Unit A A A A dB dB dB dB W W W V V W
AA A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAA A A A A A AAAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA A A A AAAAA AA AAA AAA AAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA A A AA A A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA A AAAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A AA A A A A AAAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAA AAA AAAA AAAAAAAAAAAAAAA A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAAA AAAA A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA AAAA A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA A A AA A A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAA AAAA AA A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA A A AA A A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAA AAAA AAAAAAAA AAAAAAAA A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA A A A A AA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA A A A AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA A A AAAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA AAA AAA AAAA AAAAAAAAAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAAA AAA AAAA AAAAAAAA AAAAAAAA A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AAA AAAA A AAA A A A AAAAAAAAAAAA AAAA AAAAAAA AAAAAAAA AA A A A AA A A A A
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C
Rev. A2, 09-Oct-00
Electrical Characteristics (continued)
Input impedance
Maximum input signal
Input sensitivity
Input frequency range
REF input
Tuning step
Effective scaling factor of reference divider
Effective scaling factor of programmable divider
PLL part
Control voltage for deactivated SLI
Control voltage for activated SLI
Control voltage for deactivated WAGC
Control voltage for activated WAGC
Max. gain control voltage
Min. gain control voltage
Window AGC mode charge pump current
Negative charge pump current, slow mode
Positive charge pump current, slow mode
Negative charge pump current, fast mode
Positive charge pump current, fast mode
IF AGC unit
Maximum gain control voltage
Minimum gain control voltage
Window AGC mode charge pump current
Parameters
Single ended
Internal oscillator overdriven
Internal oscillator overdriven
Internal oscillator overdriven
SLI = LOW
SLI = HIGH
WAGC = LOW
WAGC = HIGH
VWAGC = HIGH Pin 28
VWAGC = LOW, VSLI = LOW
VWAGC = LOW, VSLI = LOW
VWAGC = LOW, VSLI = HIGH
VWAGC = LOW, VSLI = HIGH
VWAGC = HIGH
Test Conditions / Pins
Preliminary Information
Pin 22 Pin 28 Pin 28 Pin 28 Pin 28 Pin 21 Pin 28 Pin 28 Pin 21 Pin 22 Pin 42 ICPIFNEG, SM ICPIFNEG, FM ICPIFPOS, SM ICPIFPOS, FM VWAGCHigh VWAGCLow VAGCIFmax VAGCIFmin ICPIFWAGC VAGCmax VAGCmin VSLIHigh VSLILow ICPRFhi Symbol SFref,eff vref,max vref,min SFeff Zref fref Min. 2048 -220 -500 144 -52 145 2.0 2.0 -4 38 5
2 || 2.5
-180
Typ.
0.75
0.75
-40
180
5.9
6.6
16
40
0
0
U2731B
32766
Max.
+500
2047
-145
300
-38AAAA A
220
0.7
0.7
+4
50
30
52
kW/pF
mVrms
mVrms
13 (20) MHz Unit kHz A A A mA nA V V V V V V V V
AAAA A A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAA AAA AAA AAA AAAAAAAAA AAAA AAAAA A A A A A A AAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAA A A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAA AA A A A A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AA A A A A AAAAAAAAAAAAAA AAAAAAAAA AAAAAAAA AA A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAA AAAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A AAAA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAA A A A A AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAA AAA AAA AAA AAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAA AA AAA AAA AAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
*) Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C
Electrical Characteristics (continued)
U2731B
14 (20) Input voltage SCL/SDA I2C bus Maximum output current Dynamic range Variation of VM Output voltage D/A converters AS1 = 1, AS2 = 1 AS1 = 1, AS2 = 0 AS1 = 0, AS2 = 1 AS1 = 0, AS2 = 0 Address selection Saturation voltage Leakage current Switches Saturation voltage Leakage current Lock indication Effective phase noise High impedance mode Charge-pump current gp p Phase detector Output voltage REF output Parameters
*)
The phase detector's phase-noise contribution to the VCO's frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz).
|VCa0-n VM/128| 70 mV, n = Caj x 2j, a = A, B, C
HIGH
Tamb = -40 to +85C
VS = 7.65 to 9.35 V
Ca7 = HIGH, Ca0 to Ca6 = LOW, a = A, B, C
ISW = 0.25 mA
IPLCK = 0.25 mA
VPLCK = 5.5 V
IPD = 203 mA
TRI = HIGH
I100 = LOW, I50 = LOW
I100 = LOW, I50 = HIGH
I100 = HIGH, I50 = LOW
I100 = HIGH, I50 = HIGH
2.7kW || 2.5pF load
Test Conditions / Pins
Preliminary Information
Pins 7, 8 and 9 Pins 3, 4 and 6 Pins 1 and 2 Pin 39 Pin 44 Pin 41 Pin 5 VLL, VUL DVM,temp VPLCK,sat ICAOmax ICBOmax ICCOmax DVM,VS Symbol IPLCK,L IPD,tri VSW,sat IPD1 vout,ref IPD2 IPD3 IPD4 ISW,L LPD VM 0.9 VS 0.4 VS 120 160 Min. 40 80 0.5 70 3 0 100 100 102 151 203 -159 open Typ. 4.25 50 50 20 Rev. A2, 09-Oct-00 0.6 VS 0.1 VS Max. t.b.d. 120 180 240 60 5.5 8.0 0.5 0.5 VS 10 dBc/Hz mVrms Unit mV mV
mA
mA
mA
mA
mA
mA
mA
nA
V V V V V
A AA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A AAAA A AAAAAAAAAAAAAA AAAAAAAAAA AAAAAAA AA A A A A A AAAA A A A A AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAA A A A A AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAAAAAAAA AA A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAA A AA A A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAAAAAAAAA AAAAAAA AA A A A A A AAAA A A A A AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A A AAAAAAAAAAAAAAA AAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAAAAAAAA AAAAAAA AA A A A A
Application Circuit
Test conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25C
Rev. A2, 09-Oct-00
Electrical Characteristics (continued)
Setup time DATA
hold time DATA
Setup time STOP
Setup time START
Hold time START
SCL LOW period
Time before new transmission can start SCL HIGH period
Fall time (SCL; SDA)
Rise time (SCL, SDA)
SCL clock frequency
Output voltage SDA (open collector)
Input voltage SCL/SDA
Switches
U2730B-B
Address select voltage
Pre- selector
C
Miro crystal 16.384 MHz CXAT-T1
C
Parameters
SDA
SCL
44
1
51k
18p
43
2
33p
42
3
8.5V
33k
76k 76k
68p
9k
41
4
9k
BC846B
ISDA = 2 mA, SDA = LOW
LOW
40
5
1.2n
10n
Test Conditions / Pins
39
8.5V
6
22k
76k
9k
Preliminary Information
38 7
100p
8.5V
33k
2.2k
100p
37
8
10n
3.3n
36
Figure 6. Application circuit
2.2k
9
4.7k
100n
100n
100n
27p
10
35
4.7p 2.2p 2.2p 4.7p
U2731B
3.3n
11
34
47nH
2.2p
BB545
RFA
12
33
1n
1n
13
32
4.7k
Symbol
RFB
14
31
thddat
tsudat
thdsta
tsustp
tsusta
thigh
tlow
tbuf
1n
1n
tf
tr
15
30
VAGCRF
16
29
3.3
17
28
Min.
10n 10n
250
3.3
4.7
4.7
4.7
4.7
0.1
0
4
4
VAGCIF
18
27
10n 10n 1n
8.5V
19
26
Typ.
20
25
Antialiasing filter
100p
21
24
220n
U2731B
22
23
10n
10n
Max.
300
100
0.4
1.5
1
680nH
SAW filter
1.8k
4.7k
AD-converter
SLI
WAGC
15 (20)
8.5V
Unit
kHz
15040
S+M X6922M
ms ms ms ms ms ms ms ms
ns V V
ns
U2731B
Application Circuits of the Reference Oscillator
OSCI 68p 33p OSCO 18p
15041
Reference divider
Reference signal 50 1n
OSCI
Reference divider
OSCO
15042
Figure 7. Oscillator operation
Figure 8. Oscillator overdriven
Measurement Circuit for Electrical Characteristics
8.5V 51k 33k BC846B 22k 100p 3.3n 3.3n 4.7k VAGCIF BB545 47n 3.3 4.7k 1k 2.2k 4.7k 1.2n 33k 27p 8.5V 10n REF IN 10n Address select voltage 44 43 42 41 10n 40 39 100p 38 37 36 47nH 4.7p 2.2p 2.2p 4.7p 35 34 33 32 31 30 29 28 10n 27 10n 26 100p 10n 24 23 50 2.2p 8.5V 10n IFIN 1.8k IFAD
C
2.2k
25
U2731B
1 2 3 4 76k 76k 5 6 76k 7 8 9 10 11 12 1n 100n 100n Switches 100n 9k 9k 9k 1n 50 1n 50 100 51 3.3 10n 10n 1n 220n 13 14 1n SLI 8.5V 15 16 17 18 19 20 21 22
SCL
WAGC
C
SDA
U2730B-B Pre- selector
8.5V RFA RFB VAGCRF O1SA
15043
Figure 9. Measurement circuit for electrical characteristics
16 (20)
Rev. A2, 09-Oct-00
Preliminary Information
U2731B
RFAGC Voltage-Generation Block Circuit
VREF VAGC,INT
IDA TBI SAW1 SAW2 D/A
BUF_IN
AGC_BP AGC_RECT AGC_TP VREF R AGC_COMP IDA TAI AGC_THRESH
SLI WAGC AGCRF voltage CPRF CHARGE PUMP CAGC
15044
D/A
Figure 10. RFAGC voltage-generation block circuit
IFAGC Voltage-Generation Block Circuit
IFAMP IFMX IFAD Antialiasing filter A/D converter
VAGC R1 IFAGC1 R2
IFAGC2 V REF CHARGE PUMP CPRF R AGC_THRESH IDA TCI
15045
AGCIF
SLI
WAGC
D/A
Figure 11. IFAGC voltage-generation block circuit
Rev. A2, 09-Oct-00
17 (20)
Preliminary Information
U2731B
VCO Circuit
VBias VS
C1VC
VTune
B2VC B1VC
C2VC
15046
Figure 12. VCO circuit
Phase-Noise Performance
(Example: SFeff = 16899, SFref,eff = 1120, fref = 17.92 MHz, IPD = 200 mA, spectrum analysis: HP7000)
10.00 dB/DIV 10.00 dB/DIV
< -70 dBc/Hz
CENTER 270.384 MHz RB 100 Hz VB 100 Hz
SPAN 10.00 kHz ST 3.050 sec
CENTER 270.384 MHz RB 1.00 kHz VB 1.00 kHz
SPAN 200.0 kHz ST 600.0 msec
Figure 13.
Figure 14.
18 (20)
Rev. A2, 09-Oct-00
Preliminary Information
U2731B
Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications 13040
1
22
Rev. A2, 09-Oct-00
19 (20)
Preliminary Information
U2731B
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
3.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
20 (20)
Rev. A2, 09-Oct-00
Preliminary Information

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